ultra low power/high speed cmos sram 2m x 8 bit BH62UV1600 bsi r0201 - b h62uv1600 revision 1.0 jul . 2005 1 n features ? wide v cc low operation voltage : 1.65v ~ 3.6v ? ultra low power consumption : v cc = 3.0v operation current : 5.0ma at 70ns at 25 o c 1.5ma at 1mhz at 25 o c standby current : 3ua at 25 o c v cc = 2.0v data retention current : 3ua at 25 o c ? high speed access time : -70 70ns at 1.8v at 85 o c ? automatic power down when chip is deselected ? easy expansion with ce1, ce2 and oe options ? three state outputs and ttl compatible ? fully static operation, no clock, no refreash ? data retention supply voltage as low as 1.0v n description the BH62UV1600 is a high performance, ultra low power cmos static random access memory organized as 2,048k by 8 bits and operates in a wide range of 1.65v to 3.6v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with typical operating current of 1.5ma at 1mhz at 3.6v/25 o c and maximum access time of 70ns at 1.8v/85 o c. easy memory expansion is provided by an active low chip enable (ce1), an active high chip enable (ce2) and active low output enable (oe) and three-state output drivers. the BH62UV1600 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the BH62UV1600 is made with two chips of 8mbit sram by stacked multi-chip-package. the BH62UV1600 is available 48-ball bga package. n product family power consumption speed (ns) standby (i ccsb1 , max) operating (i cc , max) product family operating temperature v cc range v cc =1.8~3.6v v cc =3.6v v cc =1.8v v cc =3.6v v cc =1.8v pkg type +0 o c to +70 o c 70 20ua 15ua 10ma 7ma BH62UV1600ai -25 o c to +85 o c 1.65v ~ 3.6v 70 25ua 20ua 10ma 7ma bga-48-0608 n pin configurations n block diagram brilliance semiconductor, inc. reserves the right to modify document contents without notice. detailed product characteristic test report is available upon request and being accepted. g h f e d c b a 1 2 3 4 5 6 a9 a11 a10 a19 a12 a14 a13 a15 we nc nc nc dq7 a17 a16 a7 vss vcc dq2 dq1 dq6 dq5 vss a5 oe a3 a0 a6 a4 a1 a2 ce2 nc nc nc ce1 d04 nc 48-ball bga top view nc nc dq0 vss vcc d3 nc a18 a20 a8 address input buffer row decoder memory array 1024 x 16384 column i/o write driver sense amp column decoder address input buffer a 15 a 13 a 16 a 2 a 1 data input buffer control dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a 12 a11 a10 a9 a8 a7 a6 a5 a4 a3 8 8 8 8 11 2048 16384 1024 10 a 17 a 19 data output buffer a 14 ce1 ce2 we oe v cc gnd a 0 a 20 a 18
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 2 n pin descriptions name function a0-a20 address input these 21 address inputs select one of the 2,048k x 8 bit in the ram ce1 chip enable 1 input ce2 chip enable 2 input ce1 is active low and ce2 is active high. both chip enables must be active when data read from or write to the device. if either chip enable is not active, the device is deselected and is in standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations . with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write en able is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impendence state when oe is inactive. dq0-dq7 data input/output ports 8 bi-directional ports are used to read data from or write data into the ram. v cc power supply v ss ground n truth table mode ce1 ce2 we oe i/o operation v cc current h x x x chip de-selected (power down) x l x x high z i ccsb , i ccsb1 output disabled l h h h high z i cc read l h h l d out i cc write l h l x d in i cc notes: h means v ih ; l means v il ; x means don t care (must be v ih or v il state) n absolute maximum ratings (1) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 (2) to 4.6v v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. C 2.0v in case of ac pulse width less than 30 ns n operating range rang ambient temperature v cc commercial 0 o c to + 70 o c 1.65v ~ 3.6v industrial -25 o c to + 85 o c 1.65v ~ 3.6v n capacitance (1) (t a = 25 o c, f = 1.0mhz) symbol pamameter conditions max. units c in input capacitance v in = 0v 10 pf c io input/output capacitance v i/o = 0v 15 pf 1. this parameter is guaranteed and not 100% tested.
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 3 n dc electrical characteristics (t a = -25 o c to +85 o c) parameter name parameter test conditions min. typ. (1) max. units v cc power supply 1.65 -- 3.6 v v cc =1.8v 0.4 v il input low voltage v cc =3.6v -0.3 (2) -- 0.8 v v cc =1.8v 1.4 v ih input high voltage v cc =3.6v 2.0 -- v cc +0.3 (3) v i il input leakage current v in = 0v to v cc , ce1 = v ih or ce2 = v il -- -- 1 ua i lo output leakage current v i/o = 0v to v cc , ce1 = v ih or ce2 = v il or oe = v ih -- -- 1 ua v cc = max, i ol = 0.1ma v cc =1.8v 0.2 v ol output low voltage v cc = max, i ol = 2.0ma v cc =3.6v -- -- 0.4 v v cc = min, i oh = -0.1ma v cc =1.8v v cc -0.2 v oh output high voltage v cc = min, i oh = -1.0ma v cc =3.6v 2.4 -- -- v v cc =1.8v 4.5 7 i cc operating power supply current ce1 = v il , ce2 = v ih , i dq = 0ma, f = f max (4) v cc =3.6v -- 5.0 10 ma v cc =1.8v 1.0 1.5 i cc1 operating power supply current ce1 = v il and ce2 = v ih , i dq = 0ma, f = 1mhz v cc =3.6v -- 1.5 2.0 ma v cc =1.8v 0.5 i ccsb standby current C ttl ce1 = v ih , or ce2 = v il , i dq = 0ma v cc =3.6v -- -- 1.0 ma v cc =1.8v 3.0 20 i ccsb1 (5) standby current C cmos ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v v cc =3.6v -- 3.0 25 ua 1. typical characteristics are at t a =25 o c. 2. undershoot: -1.0v in case of pulse width less than 20 ns. 3. overshoot: v cc +1.0v in case of pulse width less than 20 ns. 4. f max =1/t rc. 5. i ccsb1(max.) is 15ua/20ua at v cc =1.8v/3.6v and t a =0 o c ~ 70 o c. n data retention characteristics (t a = -25 o c to +85 o c) symbol parameter test conditions min. typ. (1) max. units v dr v cc for data retention ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v 1.0 -- -- v v cc =1.0v 1.0 7.0 i ccdr (3) data retention current ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v v cc =2.0v -- 3.0 20 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns 1. t a =25 o c. 2. t rc = read cycle time. 3. i ccdr(max.) is 6.0ua/15ua at v cc =1.0v/2.0v and t a =0 o c ~ 70 o c. n low v cc data retention waveform (1) (ce1 controlled) data retention mode v cc t cdr v cc t r v ih v ih ce1 R v cc - 0.2v v dr R 1.0v ce1 v cc
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 4 n low v cc data retention waveform (2) (ce2 controlled) n ac test conditions (test load and input/output reference) input pulse levels v cc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc t clz1 , t clz2 , t olz , t chz1 , t chz2 , t ohz , t whz , t ow c l = 5pf+1ttl output load others c l = 30pf+1ttl 1. including jig and scope capacitance. n key to switching waveforms waveform inputs outputs must be steady must be steady may change from h to l will be change from h to l may change from l to h will be change from l to h don t care any change permitted change : state unknow does not apply center line is high inpedance off state n ac electrical characteristics (t a = -25 o c to +85 o c) read cycle cycle time : 70ns jedec parameter name paraneter name description min. typ. max. units t avax t rc read cycle time 70 -- -- ns t avqx t aa address access time -- -- 70 ns t e1lqv t acs1 chip select access time (ce1) -- -- 70 ns t e2lqv t acs2 chip select access time (ce2) -- -- 70 ns t glqv t oe output enable to output valid -- -- 30 ns t e1lqx t clz1 chip select to output low z (ce1) 10 -- -- ns t e2lqx t clz2 chip select to output low z (ce2) 10 -- -- ns t glqx t olz output enable to output low z 5 -- -- ns t e1hqz t chz1 chip select to output high z (ce1) -- -- 25 ns t e2hqz t chz2 chip select to output high z (ce2) -- -- 25 ns t ghqz t ohz output enable to output high z -- -- 25 ns t avqx t oh data hold from address change 10 -- -- ns c l (1) 1 ttl output all input pulses ? ? 90 % v cc gnd rise time: 1v/ns fall time: 1v/ns 90% ? ? 10% 10% ce2 data retention mode v cc t cdr v cc t r v il v il v cc v dr R 1.0v ce2 Q 0.2v
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 5 n switching waveforms (read cycle) read cycle 1 (1,2,4) read cycle 2 (1,3,4) read cycle 3 (1, 4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce1 = v il and ce2= v ih . 3. address valid prior to or coincident with ce1 transition low and/or ce2 transition high. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. t rc t oh t aa d out address t oh t clz (5) d out ce2 ce1 t acs2 t acs1 t chz1 , t chz2 (5) t oh t rc t oe t clz2 (5) t chz2 (2,5) d out ce2 ce1 oe address t clz1 (5) t acs1 t acs2 t chz1 (1,5) t ohz (5) t olz t aa
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 6 n ac electrical characteristics (t a = -25 o c to +85 o c) write cycle cycle time : 70ns jedec parameter name paraneter name description min. typ. max. units t avax t wc write cycle time 70 -- -- ns t avwl t as address set up time 0 -- -- ns t avwh t aw address valid to end of write 50 -- -- ns t elwh t cw chip select to end of write 50 -- -- ns t wlwh t wp write pulse width 35 -- -- ns t whax t wr1 write recovery time (ce1, we) 0 -- -- ns t e2lax t wr2 write recovery time (ce2) 0 -- -- ns t wlqz t whz write to output high z -- -- 20 ns t dvwh t dw data to write time overlap 30 -- -- ns t whdx t dh data hold from write time 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 25 ns t whqx t ow end of write to output active 5 -- -- ns n switching waveforms (write cycle) write cycle 1 (1) t wc t wr1 (3) t cw (11) t cw (11) t wp (2) t aw t ohz (4,10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 oe address (5) (5)
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 7 write cycle 2 (1,6) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce1 and ce2 active and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce1 or we going high or ce2 going low at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce1 low transition or the ce2 high transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce1 is low and ce2 is high during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce1 going low or ce2 going high to the end of write. t wc t cw (11) t cw (11) t wp (2) t aw t whz (4,10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 address (5) (5) t ow (7) (8) (8,9)
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 8 n ordering information note: brilliance semiconductor inc. (bsi) assumes no responsibility for the application or use of any product or circuit described herein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n package dimensions package a : bga-48-0608 BH62UV1600 x x z y y grade i: -25 o c ~ +85 o c speed 70: 70ns pkg material -: normal g: green 48 mini-bga (6 x 8) d1 view a 1 . 4 m a x . e e 1 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. 3: symbol "n" is the number of solder balls. ball pitch e = 0.75 d 8.0 6.0 e n 48 3.75 e1 d1 5.25 notes:
bsi b h 6 2u v 1600 r0201-BH62UV1600 revision 1.0 jul. 2005 9 n revision history revision no. history draft date remark 1.0 initial production version july 15,2005 initial
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